Tribology challenges for nanolithography

Computer chips are the building blocks of all modern technology. The next generation of computer chips therefore have the potential to make nearly all sectors of our economy faster and more efficient. One of the most critical challenges in high-end chip production is friction and wear. Stresses and deformations that build up during wafer clamping -and result from friction between the wafer and the wafer table- limit the precision with which the wafers can be patterned, in turn limiting the number of transistors that fit onto a single chip, which translates into memory or computing power of devices. Future chip production requires control over frictional slip at the scale of atomic spacings and nearly zero wear over millions of clamping cycles. However, what controls macroscopic friction and wear at the atomic level remains elusive, hampering our ability to produce solutions. This symposium brings together international experts in nanotribology and is aimed at discussing fundamental research on friction and wear in relation to the friction and wear related challenges in nanolithography.